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An area‐efficient switched‐capacitor relaxation oscillator with digitally controlled frequency tunability
Author(s) -
Ausín José L.,
Ramos J.,
Torelli G.,
DuqueCarrillo J. F.
Publication year - 2009
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.542
Subject(s) - jitter , relaxation oscillator , switched capacitor , capacitor , cmos , capacitance , electronic engineering , voltage controlled oscillator , digitally controlled oscillator , phase noise , electrical engineering , oscillation (cell signaling) , vackář oscillator , delay line oscillator , computer science , engineering , phase locked loop , physics , voltage , local oscillator , electrode , quantum mechanics , biology , genetics
Abstract This paper describes a programmable low‐jitter switched‐capacitor (SC) square‐wave oscillator for the use in a variety of voice‐band signal‐processing applications. The core of the circuit is a relaxation oscillator whose oscillation frequency programmability does not resort to variations either in capacitor values or in the sampling frequency. As a result, total capacitance is reduced and, hence, silicon area is minimized while low phase jitter and high resolution programmability are achieved. Simulation results referred to the design of an SC oscillator in 0.35‐µm CMOS technology are presented to demonstrate the feasibility of the proposed approach. Copyright © 2008 John Wiley & Sons, Ltd.