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A dc I – V model for short‐channel polygonal enclosed‐layout transistors
Author(s) -
López Paula,
Hauer Johann,
BlancoFilgueira Beatriz,
Cabello Diego
Publication year - 2009
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.537
Subject(s) - nmos logic , transistor , cmos , channel (broadcasting) , chip , channel length modulation , electronic engineering , engineering , electrical engineering , computer science , mosfet , voltage
Despite the demonstrated radiation immunity of gate‐enclosed layout transistors in deep submicron CMOS technologies, there is a significant lack of a thorough theoretical study addressing fundamental design issues on this kind of transistors. In this paper we propose a physical dc I – V model for short‐channel polygonal‐shape enclosed‐layout transistors in both the linear and saturation regions of operation accounting for second‐order effects such as depletion region non‐uniformity, carrier velocity and channel length modulation. The impact of this layout style on the driving capability of the devices is also investigated. Experimental results based upon a fabricated NMOS test chip containing these devices in a standard 0.18µm CMOS technology process are presented. The comparison of the theoretical prediction with the experimental data show close agreement. Copyright © 2008 John Wiley & Sons, Ltd.