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Input mapping algorithm for parallel transistor structures
Author(s) -
Nikolaidis Spiridon
Publication year - 2009
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.522
Subject(s) - transistor , algorithm , cmos , computer science , set (abstract data type) , point (geometry) , electronic circuit , electronic engineering , mathematics , engineering , electrical engineering , voltage , geometry , programming language
A new algorithm for mapping every possible input pattern of a parallel transistor structure to an equivalent set of normalized inputs (having the same starting and ending point) is introduced. This algorithm is based on the analysis of the operation of the transistor structure and can be used for the development of analytical timing models for CMOS circuits. Simulation results show a very good accuracy of the algorithm. Copyright © 2008 John Wiley & Sons, Ltd.