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A new efficient dcvs circuit synthesis technique used for an improved implementation of a serial/parallel multiplier
Author(s) -
Karoubalis Theodore,
Adaos Kostas,
Alexiou George Ph.,
Kanopoulos Nick
Publication year - 1995
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.4490230604
Subject(s) - computer science , binary decision diagram , multiplier (economics) , cascode , very large scale integration , electronic circuit , computer hardware , algorithm , electronic engineering , embedded system , engineering , electrical engineering , bandwidth (computing) , amplifier , computer network , economics , macroeconomics
This paper describes an efficient technique for the design of fault‐secure VLSI circuits based on differential cascode voltage switch (DCVS) logic. We propose a new synthesis method for constructing DCVS circuits with a near‐optimal transistor count based on binary decision diagrams (BDDs). the time and memory resources required are very low, making the technique practical even for PC‐based synthesis tools. This method is the basis for a CAD tool that allows automatic synthesis of fault‐secure circuits based on the DCVS technology. We finally present an improved design and implementation of a 2's complement serial/parallel multiplier as an application of the proposed technique and algorithm.