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On algorithms in the parallel design of logic and layout of circuits with functional blocks
Author(s) -
Szolgay Peter
Publication year - 1992
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.4490200407
Subject(s) - computer science , schematic , truth table , representation (politics) , algorithm , table (database) , combinational logic , electronic circuit , register transfer level , interconnection , sequential logic , circuit extraction , logic synthesis , circuit design , page layout , physical design , parallel computing , logic gate , electronic engineering , equivalent circuit , engineering , embedded system , data mining , voltage , politics , law , political science , advertising , business , computer network , electrical engineering
Some algorithms in an experimental design methodology for circuits with combinatorial logic blocks are described in which the circuit schematics and the layout of the blocks are designed in parallel. A combinational circuit is represented by three parallel descriptions, namely the functional (truth table), the incidence (connections) and the one‐dimensional layout. to support this design method, new types of algorithms have been developed for the component extraction and interconnection phases, enabling the interactive design activity of ‘twin’ designers. the two‐dimensional layout—which is a fourth representation—of the whole circuit is generated using the one‐dimensional layout model.