Premium
Parametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models
Author(s) -
Yu T. K.,
Kang S. M.,
Sacks J.,
Welch W. J.
Publication year - 1991
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.4490190606
Subject(s) - parametric statistics , quadratic equation , cmos , electronic circuit , circuit design , computer science , integrated circuit , electronic engineering , yield (engineering) , bottleneck , circuit extraction , algorithm , equivalent circuit , mathematics , engineering , electrical engineering , statistics , voltage , materials science , geometry , metallurgy , embedded system , operating system
A major bottleneck in the design and parametric yield optimization of CMOS integrated circuits lies in the high cost of the circuit simulations. One method that significantly reduces the simulation cost is to approximate the circuit performances by fitted quadratic models and then use these computationally inexpensive models to optimize the parametric yield. In this paper quadratic statistical circuit performance models are applied to maximize the parametric yield of CMOS analogue circuits. It is found that quadratic polynomials may not always model the circuit performances well. However, with engineering knowledge applied to identify and reduce the causes of the errors, accurate performance models and yield maximization can be achieved with a reasonably small number of circuit simulations, as illustrated through examples. Distinctions between the present method and previous applications of quadratic modelling to statistical circuit design are made.