Premium
The Parametric Yield Enhancement of Integrated Circuits
Author(s) -
Singha Miran,
Spence Robert
Publication year - 1991
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.4490190605
Subject(s) - electronic circuit , context (archaeology) , integrated circuit , parametric statistics , cmos , process (computing) , yield (engineering) , electronic engineering , computer science , circuit design , topology (electrical circuits) , engineering , mathematics , electrical engineering , materials science , paleontology , statistics , metallurgy , biology , operating system
Even where a satisfactory circuit design has been achieved, it is often the case that, owing to variations in the manufacturing process, some of the samples of a mass‐produced circuit will violate the specifications on performance so that the manufacturing yield is less than 100%. Such an undesirable effect can, however, be minimized or even eliminated by redesign of the circuit to the extent of changing parameter values while retaining the original circuit topology. For discrete component circuits algorithms are available to achieve such redesign. the special characteristics of integrated circuits, however, are such that these methods are unsuitable as they stand. Two new algorithms for handling the yield enhancement of integrated circuits are described and their successful application is illustrated in the context of two‐stage CMOS op amps.