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Dynamic partitioning method for piecewise‐linear VLSI circuit simulation
Author(s) -
Tejayadi O.,
Hajj I. N.
Publication year - 1988
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.4490160409
Subject(s) - very large scale integration , computer science , convergence (economics) , electronic circuit , piecewise linear function , process (computing) , relaxation (psychology) , electrical element , algorithm , speedup , piecewise , parallel computing , network analysis , transient (computer programming) , equivalent circuit , mathematics , embedded system , engineering , electrical engineering , voltage , geometry , economics , economic growth , operating system , psychology , social psychology , mathematical analysis
This paper presents a method for dynamically partitioning circuit equations for time‐point relaxation‐based electrical circuit simulation techniques. the non‐linear element characteristics are approximated by piecewise‐linear (PWL) functions. the dynamic partitioning is carried out at every iteration during the solution process by comparing integers representing region numbers in the PWL functions, and only those PWL elements that change regions are involved in the repartitioning process. In many instances the circuit is automatically partitioned into completely d.c.‐disconnected subcircuits, which result in speeding up the convergence of the relaxation process. the approach has been implemented in a computer program for transient analysis of MOS VLSI circuits. Computational speeds of two orders of magnitude or more as compared to standard circuit simulation have been observed in solving small circuits on a serial computer without much loss in accuracy. the speed improvement is expected to be higher as the size of the circuit increases. Simulation using the dynamic partitioning method on a parallel computer indicates an efficient use of the processors, and corresponding improvement in speed.