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Defect‐tolerant nanoelectronic pattern classifiers
Author(s) -
Lee Jung Hoon,
Likharev Konstantin K.
Publication year - 2007
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.410
Subject(s) - nanodevice , synaptic weight , neuromorphic engineering , computer science , binary number , set (abstract data type) , artificial neural network , algorithm , fidelity , pattern recognition (psychology) , artificial intelligence , materials science , mathematics , nanotechnology , telecommunications , arithmetic , programming language
Mixed‐signal neuromorphic networks (‘CrossNets’), based on hybrid CMOS/nanodevice circuits, may provide unprecedented performance for important pattern classification tasks. The synaptic weights necessary for such tasks may be imported from an external ‘precursor’ network with either continuous or discrete synaptic weights (in the former case, with the quantization—‘clipping’—due to the binary character of the elementary synaptic nanodevices—latching switches.) Alternatively, the weights may be adjusted ‘ in situ ’ (inside the CrossNet) using a pseudo‐stochastic method, or set‐up using a mixed‐mode method partly employing external circuitry. Our calculations have shown that CrossNet pattern classifiers, using any of these synaptic weight adjustment methods, may be remarkably resilient. For example, in a CrossNet with synapses in the form of two small square arrays with 4 × 4 nanodevices each, the resulting weight discreteness may have a virtually negligible effect on the classification fidelity, while the fraction of defective devices which affects the performance substantially ranges from ∼20% to as high as 90% (!), depending on the training method. Copyright © 2007 John Wiley & Sons,Ltd.