Premium
A magnetoelectronic register file cell for a self‐checkpointing microprocessor
Author(s) -
Navale Nitin,
Lundgren Erica,
Carter Nicholas P.
Publication year - 2007
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.406
Subject(s) - register file , microprocessor , computer science , operating system , processor register , embedded system , register (sociolinguistics) , computer hardware , parallel computing , semiconductor memory , instruction set , memory address , linguistics , philosophy
A self‐checkpointing microprocessor periodically copies the state of the currently executing program to on‐chip non‐volatile storage, allowing it to resume execution of the program at the last checkpoint after a power supply interruption or shutdown. In this paper, we present a register file cell for a self‐checkpointing microprocessor that integrates a magnetoelectronic non‐volatile memory cell into a register cell similar to the one used in the Itanium 2 microprocessor. Our design allows the contents of each bit in the register file to be checkpointed simultaneously, reducing the time required to take a checkpoint to a few clock cycles, without compromising the performance of the register file during normal read and write operations. Because the area of the base register file cell is determined by the wiring tracks it requires, adding self‐checkpointing to the cell only increases its area by 6%. Similarly, adding self‐checkpointing has effectively no impact on the cell's performance, only increasing read and write times from299 to 300 ps, even when the additional load on the bit lines from the larger cells is considered. Copyright © 2007 John Wiley & Sons, Ltd.