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Dense CMOS implementation of a binary‐programmable cellular neural network
Author(s) -
Flak Jacek,
Laiho Mika,
Paasio Ari,
Halonen Kari
Publication year - 2006
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.365
Subject(s) - computer science , template , artificial neural network , cellular neural network , binary number , digital electronics , cmos , chip , computer hardware , computation , computer architecture , transient (computer programming) , process (computing) , parallel computing , computer engineering , electronic circuit , algorithm , electronic engineering , arithmetic , artificial intelligence , mathematics , engineering , programming language , telecommunications , electrical engineering
Abstract An implementation of a cellular neural/non‐linear network (CNN) for processing black‐and‐white (B/W) images is presented in which the template terms are 1‐bit programmable. Such approach leads to a very compact implementation of the coefficient circuits and fast (digital) programming. In this programming scheme, the more complex templates are split into subtasks that are run successively. The structure allows a direct or algorithmic evaluation of the majority of templates proposed for B/W images. The transient mask is utilized in performing the local logic operations as well as in template operations. The proposed architecture is suitable for high‐density implementations. A test structure of a 4 × 4 network has been implemented with a standard digital 0.18‐µm CMOS process. One cell occupies only 155 µm 2 , making possible the implementations of very large networks on a single chip. The algorithms used for the logic function computations and selected template evaluations are described, and the corresponding measurement results are shown. Copyright © 2006 John Wiley & Sons, Ltd.