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Design and implementation of a hybrid DPWM under 50 ps resolution based on general‐purpose FPGA
Author(s) -
Yu Limin,
Xu Shen,
Zhang Huaxin,
Shi Longxing,
Sun Weifeng
Publication year - 2021
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2898
Subject(s) - field programmable gate array , multiplexer , electronic engineering , pulse width modulation , computer science , engineering , electrical engineering , voltage , computer hardware , multiplexing
Summary High‐resolution pulse width modulators are used widely in different fields of electrical engineering, such as dimming of light‐emitting diode (LED) lighting, motor control, RF modulators, audio amplifiers, and switch‐mode power supplies. To realize a high‐resolution digital pulse‐width modulator (DPWM) in a limited inner system clock, a simple implementation of a hybrid DPWM with the resolution under 50 ps based on a general‐purpose field‐programmable gate array (FPGA) is described. The multiplexer device implementing the fast carry‐chain path and an AND gate controlling the selection input are used as a delay unit. The manual routing or placement is not required in the proposed approach, which just needs some conditional constraints. Some different conditional constraints influencing the monotonicity and resolution of DPWM are discussed. Finally, a 1 MHz switching frequency DPWM with 40 ps resolution is experimentally demonstrated, with high monotonicity and linearity. Further, a synchronous buck with and without this high‐resolution DPWM is experimentally compared to illustrate the regulation resolution.