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A high‐resolution hybrid digital pulse width modulator with dual‐edge‐triggered flip‐flops and hardware compensation
Author(s) -
Cheng Xin,
Li Bin,
Zhu Haowen,
Zhang Yongqiang,
Zhang Zhang
Publication year - 2021
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2885
Subject(s) - pulse width modulation , duty cycle , field programmable gate array , compensation (psychology) , flip flop , electronic engineering , computer science , enhanced data rates for gsm evolution , linearity , computer hardware , engineering , voltage , electrical engineering , telecommunications , psychology , psychoanalysis
Summary In this paper, a hybrid architecture of digital pulse width modulator (DPWM) which applies a counter, a phase‐shifted circuit, and a carry chain is proposed. Dual‐edge‐triggered flip‐flops are used in the phase‐shifted circuit to generate signals with 45° phase shift, which not only improves the resolution of the DPWM but also reduces the resource consumption in the carry chain. Furthermore, a hardware compensation method is used to solve the duty cycle increment phenomenon that affects the regulation accuracy of converter. An 11‐bit DPWM with the proposed architecture is implemented and tested by Xilinx Artix‐7 FPGA. The experimental results show a high resolution of 32 ps and a good linearity where R 2 is 0.99 and verify the effect of duty cycle compensation.