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A three‐phase inverter circuit using half‐bridge cells and T‐NPC for medium‐voltage applications
Author(s) -
Tirupathi Abhilash,
Annamalai Kirubakaran,
Veeramraju Tirumala Somasekhar
Publication year - 2020
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2833
Subject(s) - inverter , topology (electrical circuits) , capacitor , voltage , network topology , h bridge , three phase , computer science , engineering , electrical engineering , electronic engineering , operating system
Summary Three‐phase single DC‐source based multilevel inverter topologies play a pivotal role in industrial applications due to the reduced number of components and higher efficiency. This paper emphasizes the inverter for medium‐voltage applications that employ a conventional three‐phase T‐type structure (T‐NPC). The primary circuit of the proposed configuration consists of a T‐NPC structure connected to the half‐bridge cells at the top and the bottom sides of each phase. The secondary circuit consists of DC‐link capacitors whose voltage balancing is attained through a separate voltage balancing circuit (VBC). Using the proposed configuration, the number of components and independent DC supplies are reduced compared with the conventional topologies such as a neutral point clamped (NPC) inverter, a flying capacitor (FC) inverter, and a cascaded H‐bridge (CHB) inverter for the same number of output voltage levels. Hence, the proposed topology results in the reduction of weight, volume, and power losses of the inverter. A sine‐triangle comparison method is employed in the field programmable gate array (FPGA) platform to generate the firing pulses of the circuit switches. The effectiveness of the proposed topology is verified with simulation studies and is experimentally validated with a scaled‐down prototype.