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An improved charge‐sharing elimination pseudo‐domino logic
Author(s) -
Ghimiray Sapna Rani,
Meher Preetisudha,
Dutta Pranab Kishore
Publication year - 2020
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2798
Subject(s) - domino logic , noise margin , computer science , charge sharing , domino , dissipation , voltage , electronic engineering , electrical engineering , control theory (sociology) , materials science , transistor , engineering , physics , pass transistor logic , biochemistry , chemistry , control (management) , artificial intelligence , thermodynamics , catalysis
Summary In low‐power digital circuit, the deviation of node voltage from nominal value due to charge‐sharing leads to erroneous output. This problem is more prominent in domino logic when the device is scaled down. The scaling of the device involves scaling of threshold voltage, resulting in high leakage, less robustness and degradation in noise margin. The paper proposes an improved domino approach in terms of reduced leakage, low power dissipation and better noise margin. The stacking effect and pseudo buffer are used in precharge phase to control the gate‐to‐source voltage of pull‐down network for less power consumption and increase in performance in terms of speed of operation. A modified keeper is introduced to reduce the charge‐sharing problem. The proposed domino approach is tested against area overhead, ageing and process, voltage and temperature variation. The circuit is simulated using Cadence Virtuoso Spectre for 90 nm technology. The results obtained from the simulation represent the usefulness of the proposed circuit in terms of power dissipation, stability due to temperature variation, leakage due to temperature variation and delay. The result also shows that the circuit is less prone to charge redistribution problem that exist in domino circuit.