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Efficient implementation of mixed‐precision multiply‐accumulator unit for AI algorithms
Author(s) -
Mounica Chandana,
Krishna Sagar,
Veeramachaneni Sreehari,
Mahammad S Noor
Publication year - 2020
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2776
Subject(s) - adder , accumulator (cryptography) , hydraulic accumulator , computer science , double precision floating point format , algorithm , carry (investment) , floating point , computer hardware , arithmetic , arithmetic logic unit , computer engineering , mathematics , engineering , latency (audio) , mechanical engineering , telecommunications , finance , economics
Summary Many of the modern deep learning, machine learning, and artificial intelligence algorithms use adders, multipliers, and multiply‐accumulators (MACs) with mixed precisions. In general, fixed‐point and floating‐point adders, multipliers, and MACs are used in mixed‐precision hardware, such that the above algorithm can choose appropriate hardware for its processing. This paper proposes an efficient mixed‐precision MAC circuit that can perform fixed‐point and floating‐point operations. The proposed design uses Han‐Carlson adder with late carry or end‐around carry in its accumulator design; as a result, delay and energy of the circuit reduce by 21 . 46 % and 22 . 54 % respectively, when compared with the existing designs from the literature.