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An efficient circuit for error reduction in logarithmic multiplication for filtering applications
Author(s) -
Joginipelly Arjun Kumar,
Charalampidis Dimitrios
Publication year - 2020
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2775
Subject(s) - multiplication (music) , logarithm , reduction (mathematics) , computer science , filter (signal processing) , arithmetic , multiplication algorithm , digital filter , signal processing , computer hardware , algorithm , digital signal processing , mathematics , computer vision , mathematical analysis , geometry , combinatorics , binary number
Summary Real‐time digital signal and image processing applications, such as filtering, demand high performance. Often, multiplication is one of the most time‐consuming steps of the filtering operation. Log‐based multipliers have been used for improving multiplication efficiency at the expense of accuracy. The objective of the proposed work is to improve the accuracy of log‐based hardware multipliers by appropriately altering the filter weights and without increasing the required resources.