Premium
Design of high throughput asynchronous FIR filter using gate level pipelined multipliers and adders
Author(s) -
Sravani K,
Rao Rathnamala
Publication year - 2020
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2771
Subject(s) - finite impulse response , computer science , asynchronous communication , adder , latency (audio) , pipeline (software) , digital filter , throughput , cascaded integrator–comb filter , filter (signal processing) , electronic engineering , computer hardware , root raised cosine filter , algorithm , engineering , telecommunications , wireless , computer vision , programming language
Summary This work presents the design of an asynchronous digital finite impulse response (FIR) filter suitable for high‐performance partial response maximum likelihood (PRML) read channel ICs. A high throughput, low latency FIR filter is the basic requirement for the equalization process in read channels. To achieve the enhancement in speed and reduction in latency of the FIR filter, its computational units are deeply pipelined using high‐capacity hybrid (HC‐hybrid) logic pipeline method. The designed FIR filter has been simulated using UMC‐180 nm and UMC‐65 nm technologies. Simulation results show that the asynchronous digital FIR filter can operate up to a throughput of 1.17 Giga items/s in 180 nm and 2.3 Giga items/s in 65 nm technology yet with the latency in the order of ns.