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A 6th‐order 75 dB‐DR 10.7 MHz 3.3 V CMOS bandpass ΣΔ modulator sampled at 37.05 MHz
Author(s) -
Cusinato Paolo,
Stefani Fabrizio,
Baschirotto Andrea
Publication year - 2004
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.277
Subject(s) - intermodulation , cmos , bandwidth (computing) , dynamic range , electrical engineering , band pass filter , delta sigma modulation , switched capacitor , electronic engineering , capacitor , telecommunications , computer science , engineering , amplifier , voltage
This paper describes the design and the implementation of a 6th‐order bandpass ΣΔ modulator to be used for IF digitizing at 10.7 MHz of a broadcasting FM radio signal. The modulator is sampled at 37.05 MHz. This sampling frequency value allows to optimize both modulator and overall receiver channel performance. The modulator has been implemented in a standard double‐poly 0.35 µm CMOS technology using switched capacitor (SC) technique and consumes 116 mW from a single 3.3 V power supply. The modulator features 75 dB dynamic range and 66 dB peak‐SNR within a 200 kHz bandwidth (FM bandwidth). Third‐order intermodulation products are suppressed by –78dBc. Copyright © 2004 John Wiley & Sons, Ltd.