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A closed loop inductorless equalizer with a modified analysis of power comparator behaviour
Author(s) -
Talluri Govardhana Rao,
Shojaei Baghini Maryam
Publication year - 2020
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2749
Subject(s) - adaptive equalizer , electronic engineering , comparator , cmos , filter (signal processing) , computer science , equalizer , jitter , channel (broadcasting) , electrical engineering , engineering , voltage , telecommunications
Summary Inductorless circuits are gaining advantage in radio frequency (RF) and high‐speed serial link circuits due to the reduced silicon area. This paper presents an inductorless adaptive analog equalizer using an adaptive hybrid filter comprising integrated low pass and high pass filter. The equalizer, designed and fabricated in 180‐nm CMOS technology, is able to adjust the high‐frequency boost (HFB) and cutoff frequency of the internal filters depending on the data rate and the channel loss. The presented equalizer operates at data rates more than 4 Gbps in post‐layout simulation without electrostatic discharge (ESD) and package parasitics. For the test purposes, the equalizer has been packaged in QFN 64 pin package and hence the measurement results are up to 3.125 Gbps. The measurement results show that the equalizer is able to adapt the HFB for the channel losses as high as 5 dB. Average dissipated power of the equalizer at 3.125 Gbps is 18 mW with 1.8‐V supply. After reading this chapter you should be able to understand the merits of the proposed hybrid filter compared with the conventional RC filters in the adaptive equalizer using spectrum balancing technique; theoretical analysis and the impact of short channel effects on the performance of the power comparator; and test results of the adaptive equalizer using the proposed hybrid filter in the spectrum balancing technique.