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A new discrete wavelet transform appropriate for hardware implementation
Author(s) -
Meshkat Amin,
Dehghani Rasoul
Publication year - 2020
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2736
Subject(s) - wavelet , discrete wavelet transform , second generation wavelet transform , daubechies wavelet , lifting scheme , wavelet transform , stationary wavelet transform , finite impulse response , wavelet packet decomposition , mathematics , computer science , electronic engineering , algorithm , artificial intelligence , engineering
Summary A new method for computation of discrete wavelet transform is introduced. The impulse response of the finite impulse response (FIR) filter, as the main block in filter bank method, is realized such that orthonormal wavelet transform is achieved without using any multiplier as the most challenging part of the FIR filters. It is proved that the calculated Sobolev regularity of the proposed wavelet is higher than that of Daubechies for the same support width. Compared with most popular known wavelets, simulation results of the newly introduced wavelet for signal denoising prove remarkable advantage of our wavelet especially in terms of complexity and power consumption. The proposed wavelet and well‐known Daubechies wavelet are separately implemented on the Spartan‐6 FPGA (Field Programmable Gate Array) to compare the performance of them. The occupied slices and LUTs (Lookup Table) in realization of the proposed wavelet in comparison with those of Daubechies wavelet are decreased by 50% and 56%, respectively. Its power consumption at 100 MHz is also reduced by 86% in comparison with the Daubechies wavelet, and maximum frequency is increased by 186%. Implementation with standard cells of a 0.18‐μm CMOS (Complementary Metal Oxide Semiconductor Field Effect Transistor) technology shows 75% and 85% reduction in the power and chip area, respectively.