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Tunnel FET‐based ultralow‐power and hardware‐secure circuit design considering p‐i‐n forward leakage
Author(s) -
Japa Aditya,
Majumder Manoj Kumar,
Sahoo Subhendu K.,
Vaddi Ramesh
Publication year - 2020
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2731
Subject(s) - leakage (economics) , logic gate , leakage power , digital electronics , transmission gate , power consumption , transistor , electronic circuit , circuit design , reliability (semiconductor) , electronic engineering , electrical engineering , computer science , power (physics) , embedded system , engineering , voltage , physics , quantum mechanics , economics , macroeconomics
Summary Tunnel field‐effect transistor (TFET) exhibits significant p‐i‐n forward leakage with the increase in drain‐to‐source voltage bias, and this adversely impacts the power consumption and reliability of TFET digital circuits. This work presents low‐power circuit techniques that result in novel compact gates and recommends tristate gates to mitigate the leakage effects. The proposed novel compact gates and tristate gates demonstrate two and six times lower power consumption compared with conventional TFET transmission gates with enhanced reliability. Further, this work introduces a new design methodology that leverages TFET p‐i‐n forward leakage for hardware obfuscation applications. Utilizing the proposed design methodology, the optimization of 40% and 80% in area and power consumption of hardware security primitives like true random number generators is also accomplished.