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Charge controlled delay element enabled widely linear power efficient MPCG‐MDLL in 1.2V, 65nm CMOS
Author(s) -
Kammari Raviteja,
Pasupureddi Vijaya Sankara Rao
Publication year - 2020
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2719
Subject(s) - jitter , delay locked loop , cmos , delay calculation , topology (electrical circuits) , electronic engineering , voltage , electrical engineering , group delay and phase delay , power (physics) , propagation delay , computer science , engineering , phase locked loop , physics , filter (signal processing) , quantum mechanics
Summary In this work, a robust, low‐power, widely linear multiphase clock generation and multiplying delay‐locked loop (MPCG‐MDLL) architecture is realized, using a new differential charge‐mode delay element circuit topology. The heart of any MPCG‐MDLL architecture is the delay element, and hence, the characteristics of the delay element influence the overall performance of the MPCG‐MDLL, in terms of its specifications such as peak‐to‐peak jitter, lock range, delay range, control voltage range, and power consumption. The proposed eight‐phase MPCG‐MDLL along with the charge‐mode delay element outperforms the conventional MPCG‐MDLLs that deploy delay elements such as a current‐starved inverter (CSI), wide‐range CSI, triply controlled delay cell, digital‐controlled delay element, and the like. The eight‐phase MPCG‐MDLL along with the new charge‐mode delay element circuit topology is implemented in 1.2‐V, 65‐nm CMOS technology. The performance results show that the eight‐stage delay line has a delay range from 640 to 960 ps over the rail‐to‐rail control voltage range. The implemented MPCG‐DLL is robust over process, voltage, and temperature (PVT) corners and exhibits a lock range of 400 MHz and a peak‐to‐peak jitter of less than 60 fs for all the DLL output phases and peak‐to‐peak jitter of 0.54 and 1.24 ps for the synthesized 5‐GHz clocks for an input reference clock frequency of 1.25 GHz. The MPCG‐MDLL consumes 4.74 mW of power and occupies an area of 0.017 mm 2 .