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A mathematical method to realize complex poles in a high‐order passive switched‐capacitor filter
Author(s) -
Niaboli Guilani Mohammad,
Ardeshir Gholamreza
Publication year - 2019
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2689
Subject(s) - cmos , analogue filter , switched capacitor , filter (signal processing) , butterworth filter , capacitor , electronic engineering , noise (video) , active filter , control theory (sociology) , low pass filter , topology (electrical circuits) , engineering , electrical engineering , prototype filter , computer science , voltage , digital filter , control (management) , artificial intelligence , image (mathematics)
Summary A high‐order discrete‐time IIR low‐pass with complex poles using charge sampling is presented in a single‐stage structure by using a mathematical strategy. In comparison with the analog complex‐poles G m ‐C filters, the proposed filter consumes lower power and has good linearity, and all of the tunings are implemented only by capacitor sizes. The proposed filter is a seventh‐order Butterworth, but this method can be generalized to implement other complex pole filters like Tchebyshev and Elliptic. Post‐layout simulation results in 130‐nm complementary metal‐oxide‐semiconductor (CMOS) show an IIP3 of +18 dBm and a noise figure of 5 dB. The filter has a rejection of more than 110 dB in its stop band and consumes 1.5 mW with a 1.6‐V supply voltage, and circuit occupies an about 0.12 mm 2 of silicon.