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An efficient voltage to delay conversion method for DCVSL cells and its application in high speed all‐digital time‐based quantization
Author(s) -
Valiollahi Sepideh,
Ardeshir Gholamreza
Publication year - 2019
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2673
Subject(s) - cascode , cmos , propagation delay , electronic engineering , voltage , pmos logic , electrical engineering , quantization (signal processing) , computer science , engineering , transistor , amplifier , computer vision
Summary Translating the analog input voltage to delay of delay cells is a necessity for realizing digital time‐based quantization. Usually, this conversion is done through additional elements, imposing extra power and area. This paper proposes a voltage to delay conversion method for cross‐coupled differential cascode voltage switch logic (DCVSL) cells, without adding any extra elements to their basic structures. Cross‐coupled delay cells are superior to conventional CMOS inverters in terms of lower power consumption, propagation delay, and area. However, controlling their delay is a demanding task due to their asynchronous charging and discharging. The key features of the proposed method are (a) controlling the delay of DCVSL cells just by see‐saw changing of PMOS transistors source voltages; (b) reducing the propagation delays of DCVSL cells by simultaneously accelerating the charging and discharging processes; (c) reducing the power consumption by decreasing both the switching time and short‐circuit current; (d) employing the proposed voltage to delay conversion method to develop a low power, small area, all‐digital time‐based analog to digital converter (ADC). The proposed 4‐bit ADC, implemented in TSMC 65‐nm CMOS technology, consumes 0.37 mW at conversion speed of 2 GHz with SNDR 20.9 dB and SFDR 30.2 dB, and occupies an active area of 0.0029 mm 2 .