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Fault‐tolerant switched capacitor–based boost multilevel inverter
Author(s) -
T Ajaykumar,
Patne Nita R.
Publication year - 2019
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2671
Subject(s) - inverter , voltage , pulse width modulation , engineering , electronic engineering , grid tie inverter , capacitor , computer science , control theory (sociology) , topology (electrical circuits) , electrical engineering , maximum power point tracking , control (management) , artificial intelligence
Summary This paper proposes a fault‐tolerant switched capacitor (SC)–based boost multilevel inverter. The proposed inverter is able to convert a low‐level dc voltage into a desired ac output voltage in single‐stage power conversion. It can accomplish a high voltage gain by using multiple SC cells arrangement at reduced voltage stresses on the switching devices and passive circuit elements in the boost network. The principle of operation and steady‐state analysis of the proposed topology are presented to formulate the mathematical relationship between input dc and output ac voltage. In addition to that, the proposed inverter can also provide reliable electrical power supply at prescribed ac output voltage in the event of open‐circuit failure of power switches. The fault tolerability is realized by reconfiguring the pulse width modulation (PWM) control scheme, whereas the reduction in output voltage is compensated by the boosting characteristic of the inverter. The effectiveness of the proposed inverter has been compared with other impedance source multilevel inverters in terms of voltage gain, boosting capability, and voltage stresses. A laboratory prototype of the proposed inverter is developed for experimentation, and its operation is validated by simulation and experimental results.