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A new structure of three‐phase five‐level inverter with nested two‐level cells
Author(s) -
Tirupathi Abhilash,
Annamalai Kirubakaran,
Veeramraju Tirumala Somasekhar
Publication year - 2019
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2648
Subject(s) - inverter , matlab , topology (electrical circuits) , voltage , cascade , pulse width modulation , field programmable gate array , computer science , network topology , electronic engineering , capacitor , modulation (music) , three phase , engineering , electrical engineering , computer hardware , physics , chemical engineering , acoustics , operating system
Summary This paper presents a new structure of three‐phase five‐level inverter with a single direct current (DC) source for low‐ and medium‐voltage applications. The proposed configuration is built with a cascade connection of two‐level cells in a nested form and owns the advantages of a reduced number of passive components, total blocking voltage of the switches, and isolated DC sources. In order to make this topology attractive, a comparison is made with five‐level inverter topologies proposed for low‐ and medium‐voltage applications in recent years. The proposed circuit is powered using a single DC source and an auxiliary voltage‐balancing circuit (AVBC) to maintain the desired DC‐link capacitor voltages. A sinusoidal pulse width modulation (SPWM) scheme is implemented in field‐programmable gate array (FPGA), using Xilinx blocks developed in MATLAB/SIMULINK environment, to control the inverter switches. The performance of the proposed topology is verified through MATLAB simulation and prototype model for a step change in load. Finally, the experimental results are presented to validate the effectiveness of the proposed topology.