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Ultralow power voltage reference circuit for implantable devices in standard CMOS technology
Author(s) -
PereiraRial Óscar,
López Paula,
Carrillo Juan M.,
Brea Víctor M.,
Cabello Diego
Publication year - 2019
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2643
Subject(s) - cmos , voltage , trimming , electrical engineering , voltage reference , power (physics) , voltage divider , pmos logic , overdrive voltage , low voltage , transistor , electronic engineering , engineering , dropout voltage , physics , mechanical engineering , quantum mechanics
Summary An ultralow power CMOS voltage reference for body implantable devices is presented in this paper. The circuit core consists of only regular threshold voltage PMOS transistors, thus leading to a very reduced output voltage dispersion, defined as σ / μ , and extremely low power consumption. A mathematical model of the generated reference voltage was obtained by solving circuit equations, and its numerical solution has been validated by extensive electrical simulations using a commercial circuit simulator. The proposed solution incorporates a passive RC low‐pass filter, to enhance power supply rejection (PSR) over a wide frequency range, and a speed‐up section, to accelerate the switching‐on of the circuit. The prototype was implemented in 0.18 μ m standard CMOS technology and is able to operate with supply voltages ranging from 0.7 to 1.8 V providing a measured output voltage value of 584.2 mV at the target temperature of 36° C. The measured σ / μ dispersion of the reference voltage generated is 0.65% without the need of trimming. At the minimum supply of 0.7 V, the experimental power consumption is 64.5 pW, while the measured PSR is kept below –60 dB from DC up to the MHz frequency range.