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An accurate and power‐efficient period‐modulator‐based interface for grounded capacitive sensors
Author(s) -
Ahmadpour Bijargah Arash,
Heidary Ali,
Torkzadeh Pooya,
Nihtianov Stoyan
Publication year - 2019
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2642
Subject(s) - electronic engineering , cmos , capacitance , effective number of bits , relaxation oscillator , capacitive sensing , electrical engineering , engineering , voltage , computer science , voltage controlled oscillator , physics , electrode , quantum mechanics
Summary A low‐power and high‐resolution capacitance‐to‐period converter (CPC) based on period modulation (PM) for subnanometer displacement measurement systems is proposed. The presented circuit employs the interface developed in a previous work, “a grounded capacitance‐to‐voltage converter (CVC) based on a zoom‐in structure,” further improving its performance through a symmetrical design of the applied autocalibration technique. The scheme is based on the use of a relaxation oscillator. To minimize the error contributed by the CPC circuitry, different precision techniques such as chopping, autocalibration, and active shielding are applied. The proposed CPC is realized in a 0.18‐μm complementary metal‐oxide‐semiconductor (CMOS) technology, occupies an area of 0.5 mm 2 , and consumes 135 μA from a 2‐V power supply. In order to achieve optimal performance and avoid overdesigning, a noise estimation of various parts of the CPC has been done. Accordingly, for a 10‐pF sensor capacitance, the overall CPC demonstrates a capacitance resolution of 0.5 fF for a latency of 128 microseconds, corresponding to an effective number of bits (ENOB) of 12.5 bits and an energy efficiency of 6 pJ/step. The nonlinearity error has been evaluated as well, resulting in a less than 0.03% full‐scale span (FSS).