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ONOFIC‐based leakage reduction technique for FinFET domino circuits
Author(s) -
Magraiya Vijay Kumar,
Gupta Tarun Kumar
Publication year - 2019
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2583
Subject(s) - subthreshold conduction , leakage (economics) , electronic circuit , domino logic , transistor , electronic engineering , domino , logic gate , electrical engineering , node (physics) , materials science , engineering , computer science , voltage , pass transistor logic , chemistry , biochemistry , structural engineering , economics , macroeconomics , catalysis
Summary A new technique ON/OFf logIC (ONOFIC) is proposed in this paper for designing domino logic circuits in fin‐field effect transistor (FinFET) deep submicron technology. In this technique, a block named ONOFIC is inserted between pull‐up network (PUN) and pull‐down network (PDN) of domino circuits. The proposed technique is simulated in FinFET short gate (SG) and low power (LP) mode. The subthreshold current which plays a major role to determinate leakage power is very low in this technique. Two‐, 4‐, 8‐, and 16‐input OR gates are simulated with 32‐nm node FinFET technology. In FinFET LP mode, the subthreshold leakage power of the proposed technique is reduced by 15% to 24.3% at 25°C and reduced by 8.71% to 23.4% at 110°C compared with standard domino circuits. The subthreshold leakage power of the proposed circuit is reduced by 19.2% to 57.3% at 25°C and reduced by 17.6% to 60.7% at 110°C compared with leakage control transistor (LECTOR)‐based circuits. In FinFET SG mode, the subthreshold leakage power of the proposed technique is reduced by 7.69% to 17.7% at 25°C and reduced by 0 to 7.85% at 110°C compared with standard domino circuits. The subthreshold leakage power of the proposed circuit is reduced by 60.4% to 73.9% at 25°C and reduced by 45.1% to 65.5% at 110°C compared with LECTOR‐based circuits. The proposed technique is also efficient to reduce subthreshold leakage power in deep nanometer technology nodes from 7 to 20 nm.