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Dual loop cascode‐Miller compensation with damping factor control unit for three‐stage amplifiers driving ultralarge load capacitors
Author(s) -
Aminzadeh Hamed,
Dashti Mohammad Ali
Publication year - 2019
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2563
Subject(s) - capacitor , frequency compensation , slew rate , amplifier , cascode , cmos , capacitance , power factor , settling time , output impedance , engineering , electrical engineering , control theory (sociology) , electrical impedance , voltage , physics , computer science , step response , control (management) , electrode , quantum mechanics , control engineering , artificial intelligence
Summary An area‐efficient amplifier topology is presented for three‐stage amplifiers driving ultralarge load capacitor with reduced power consumption. It contains two high‐speed ac feedback loops made from embedded current buffers and small‐size compensation capacitors, which pushes the nondominant complex poles to very high frequencies. To further improve the stability, a local impedance damping block is embedded. At the higher frequencies, it suppresses the high resistive property at the second‐stage output, thereby increasing the damping factor of the complex poles and improving the overall gain margin. For identical bandwidth, the overall silicon area of the on‐chip compensation capacitor is therefore decreased, leading to enhanced small‐signal and large‐signal performance metrics. Coined dual loop cascode‐Miller compensation with damping factor control unit, the effectiveness of the proposed approach is investigated through simulation results in 90‐nm complementary metal‐oxide‐semiconductor (CMOS) technology. An implementation based on the proposed technique consumes a quiescent current of 17 μA from a 1.2 V voltage supply. For a load capacitance equal to 560 pF, it achieves a gain‐bandwidth frequency of 4.34 MHz, an average slew‐rate of 1.72 V/μs, and an average settling time of 0.52 μs, when the overall compensation capacitance is set to 1.55 pF. The proposed design can supply the load capacitors up to 35 nF.