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Toward implementation of associative model in real time for character recognition: A hardware architecture proposal for embedded systems
Author(s) -
VázquezCervantes Alberto,
HernándezDíaz Teresa,
CórdovaEsparza DianaMargarita,
NavaBalanzar Luciano,
SotoCajiga J. A.,
BarrigaRodríguez Leonardo,
JiménezHernández Hugo
Publication year - 2018
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2550
Subject(s) - computer science , binary number , field programmable gate array , associative property , encode , character (mathematics) , content addressable memory , reduction (mathematics) , feature (linguistics) , process (computing) , sampling (signal processing) , pattern recognition (psychology) , theoretical computer science , artificial intelligence , algorithm , artificial neural network , computer hardware , arithmetic , mathematics , biochemistry , chemistry , linguistics , geometry , philosophy , filter (signal processing) , pure mathematics , computer vision , gene , operating system
Summary This paper presents an algorithm with low computational complexity for classifying and recognizing characters based on a random sampling and high‐dimensional binary spaces for the development of real‐time applications. Character classification is performed using uniform random sampling as the feature selection process, subsequently performing encoding as binary strings. Associative memories are commonly used as general classifiers with linear criteria to discriminate between data points. In most classifiers, the ability to efficiently detect class membership depends entirely on the expressiveness of the attributes used to encode the data. Each binary pattern encodes the distinct characteristics of several glyphs. Character features are represented as elements of a high‐dimensional binary space, where a criterion of the cluster is defined under the L 1 metric. The reduction in computational complexity is analyzed. The reduction in the number of character features through random sampling techniques makes it feasible to manage all the character information in physical architectures; therefore, this approach might use resources on a hardware platform with integer operators typically implemented at the hardware‐register level. Finally, this approach is implemented in a parallel architecture Field‐Programmable Gate Array (FPGA) and tested using a Database (DB) of different fonts, including distortions, therein showing that the efficiency is comparable to the other well‐known approaches.