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Energy efficient mapping on manycore with dynamic and partial reconfiguration: Application to a smart camera
Author(s) -
Bonamy Robin,
Bilavarn Sébastien,
Muller Fabrice,
Duhem François,
Heywood Simon,
Millet Philippe,
Lemonnier Fabrice
Publication year - 2018
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2508
Subject(s) - control reconfiguration , computer science , multiprocessing , efficient energy use , embedded system , design space exploration , scheduling (production processes) , software deployment , gate array , smart camera , field programmable gate array , parallel computing , engineering , artificial intelligence , operating system , operations management , electrical engineering
Summary This paper describes a methodology to improve the energy efficiency of high‐performance multiprocessor architectures with dynamic and partial reconfiguration (DPR), based on a thorough application study in the field of smart camera technology. Field‐programmable gate arrays are increasingly being used in cameras owing to their suitability for real‐time image processing with intensive, high‐performance tasks and to the recent advances in dynamic reconfiguration that further improve energy efficiency. The approach used to best exploit DPR is based on the better coupling of 2 decisive elements in the problem of heterogeneous deployment: design space exploration and advanced scheduling. We show how a tight integration of exploration, energy‐aware scheduling, common power models, and decision support in heterogeneous DPR multiprocessor system‐on‐a‐chip mapping can be used to improve the energy efficiency of hardware acceleration. Applying this to a mobile vehicle license‐plate tracking and recognition service results in up to a 19‐fold improvement in energy efficiency compared with software multiprocessor execution (in terms of energy‐delay product) and up to more than a threefold improvement compared with a multiprocessor with static hardware acceleration (ie, without DPR).