A 1‐Gbps reference‐less burst‐mode CDR with embedded TDC in a 65‐nm CMOS process | Zendy

Wang Yuan | Zendy; Jiang Mengying | Zendy; Liu Baoguang | Zendy; Jia Song | Zendy; Zhang Xing | Zendy

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A 1‐Gbps reference‐less burst‐mode CDR with embedded TDC in a 65‐nm CMOS process

Author(s) -

Wang Yuan,

Jiang Mengying,

Liu Baoguang,

Jia Song,

Zhang Xing

Publication year - 2018

Publication title -

international journal of circuit theory and applications

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.364

H-Index - 52

eISSN - 1097-007X

pISSN - 0098-9886

DOI - 10.1002/cta.2490

Subject(s) - cmos , clock generator , burst mode (computing) , current mode logic , computer science , electronic engineering , jitter , inverter , computer hardware , electrical engineering , clock signal , engineering , voltage

Summary A reference‐less all‐digital burst‐mode clock and data recovery circuit (CDR) is proposed in the paper. The burst‐mode CDR includes a coarse and a fine time‐to‐digital converter (TDC) with embedded phase generator. A low‐power current‐starved inverter is employed as the delay unit of the fine TDC to acquire the high measurement resolution. A calibration method to diminish the inherent delay is used to reduce the quantization error of the recovery clock. The proposed CDR is fabricated in a 65‐nm CMOS process. Experiment results show that the CDR operates from 0.9 to 1.1 Gbps and have a 13‐bit consecutive identical digits (CIDs) tolerance.

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