Low‐power, latch‐based multistage time‐to‐digital converter in 65 nm CMOS technology | Zendy

Razmdideh Ramin | Zendy; Saneei Mohsen | Zendy

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Low‐power, latch‐based multistage time‐to‐digital converter in 65 nm CMOS technology

Author(s) -

Razmdideh Ramin,

Saneei Mohsen

Publication year - 2018

Publication title -

international journal of circuit theory and applications

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.364

H-Index - 52

eISSN - 1097-007X

pISSN - 0098-9886

DOI - 10.1002/cta.2468

Subject(s) - vernier scale , time to digital converter , cmos , electronic engineering , flash (photography) , computer science , power (physics) , scheme (mathematics) , computer hardware , electrical engineering , engineering , jitter , clock signal , mathematics , physics , mathematical analysis , optics , quantum mechanics , astronomy

Summary In this paper, a low‐power and high‐resolution latch‐based time‐to‐digital converter (TDC) based on a multistage scheme is proposed. The proposed multistage TDC includes coarse, middle, and fine stages. The coarse stage is a new design of the flash TDC that is implemented by latches without using the delay cell. Also, the middle stage is a new design of the Vernier TDC with employed latches. The fine stage comprises parallel latches with different input loads.

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