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A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS
Author(s) -
Chung YungHui,
Yen ChiaWei,
Tsai PeiKang
Publication year - 2018
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2424
Subject(s) - integral nonlinearity , spurious free dynamic range , successive approximation adc , linearity , cmos , dynamic range , effective number of bits , capacitor , figure of merit , differential nonlinearity , binary number , distortion (music) , electronic engineering , physics , electrical engineering , voltage , mathematics , amplifier , engineering , optoelectronics , converters , arithmetic
Summary This paper presents an energy‐efficient 12‐bit successive approximation‐register A/D converter (ADC). The D/A converter (DAC) plays a crucial role in ADC linearity, which can be enhanced by using larger capacitor arrays. The binary‐window DAC switching scheme proposed in this paper effectively reduces DAC nonlinearity and switching errors to improve both the spurious‐free dynamic range and signal‐to‐noise‐and‐distortion ratio. The ADC prototype occupies an active area of 0.12 mm 2 in the 0.18‐μm CMOS process and consumes a total power of 0.6 mW from a 1.5‐V supply. The measured peak differential nonlinearity and integral nonlinearity are 0.57 and 0.73 least significant bit, respectively. The ADC achieves a 64.7‐dB signal‐to‐noise‐and‐distortion ratio and 83‐dB spurious‐free dynamic range at a sampling rate of 10 MS/s, corresponding to a peak figure‐of‐merit of 43 fJ/conversion‐step.