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Charge‐sharing read port with bitline pre‐charging and sensing scheme for low‐power SRAMs
Author(s) -
Maroof Naeem,
Sohail Muhammad,
Shin Hyunchul
Publication year - 2017
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2311
Subject(s) - charge sharing , electrical engineering , transistor , voltage , noise (video) , computer science , port (circuit theory) , amplifier , sense amplifier , power (physics) , threshold voltage , access time , charge (physics) , noise margin , cmos , electronic engineering , physics , computer hardware , engineering , quantum mechanics , artificial intelligence , image (mathematics)
Summary In this paper, we present our decoupled differential read (DDR) port and bitline (BL) pre‐charging scheme. The proposed scheme allows the charge sharing between bitlines during the read operation. DDR port isolates the internal nodes, thus improves the read static noise margin and allows the subthreshold operation. BLs are not pre‐charged to full V DD . Read port is designed such that for the read ‘1’ operation, BL shares its charge with BLB, and for read ‘0’ operation, BL is charged toward V DD and BLB is discharged to the ground. The proposed non‐V DD BL pre‐charging and the charge‐sharing mechanism provide substantial read power savings. Virtual power rail is used to suppress the BL leakages. A dynamic voltage level shifting pre‐amplifier is used that shifts both BLs to the middle voltage and amplifies the voltage difference. Single‐ended write driver is also presented that only conditionally charges the write BL. The proposed 10‐transistor static random access memory cell using DDR provides more than 2 times read static noise margin, ~72% read power savings, and ~40% write power savings compared with the conventional six‐transistor static random access memory. Copyright © 2016 John Wiley & Sons, Ltd.