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Robust design of CMOS amplifiers oriented to settling‐time specification
Author(s) -
Giustolisi Gianluca,
Palumbo Gaetano
Publication year - 2017
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2309
Subject(s) - settling time , settling , cmos , amplifier , transistor , electronic engineering , computer science , constraint (computer aided design) , process (computing) , control engineering , engineering , electrical engineering , step response , voltage , environmental engineering , operating system , mechanical engineering
Summary In this paper, we propose a new approach for the robust design of complementary metal‐oxide‐semiconductor amplifiers based on settling‐time specifications. The approach is based on the definition of the separation factors and on the analysis of their role in the settling time. We define a design strategy for being certain that an OTA satisfies the settling‐time constraint under any statistical variation of process or design parameters. The proposed strategy is applied to the transistor level design of a two‐stage amplifier and a three‐stage one. Simulation results, in good agreement with theory, confirm the validity of the proposed approach. Copyright © 2016 John Wiley & Sons, Ltd.