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Design exploration of efficient implementation on SoC heterogeneous platform: HEVC intra prediction application
Author(s) -
Kammoun Manel,
Ben Atitallah Ahmed,
Ben Atitallah Rabie,
Masmoudi Nouri
Publication year - 2017
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2308
Subject(s) - computer science , field programmable gate array , power consumption , embedded system , coding (social sciences) , flexibility (engineering) , hardware acceleration , software , block (permutation group theory) , computer hardware , power (physics) , operating system , statistics , physics , geometry , mathematics , quantum mechanics
Summary The relationship between CPU and hardware accelerator is critical especially in some systems that require intensive tasks and large amount of data to deal with such as video coding systems. This cooperation provides significant improvements in run‐time speed and power consumption. As software (SW) and hardware (HW) solutions provide better flexibility and performance, HW/SW implementation has emerged as a more efficient and desirable methodology for real‐time implementation. In order to evaluate different implementation methods (SW) and (HW/SW) in terms of power consumption, run‐time and area cost, we choose the Xilinx Zynq‐based FPGA as a target to perform some hardware acceleration tasks. In this case, we choose to accelerate the intra prediction block because it is one of the most complex modules defined in the high efficiency video coding decoder chain. Experimental results show that HW/SW accelerations are more than 50% improved in term of run‐time speed relative to SW modules. Moreover, the power consumption of HW/SW designs is saved by nearly 80% compared with SW cases. Copyright © 2016 John Wiley & Sons, Ltd.