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Low‐leakage sub‐threshold 9 T‐SRAM cell in 14‐nm FinFET technology
Author(s) -
Zeinali Behzad,
Madsen Jens Kargaard,
Raghavan Praveen,
Moradi Farshad
Publication year - 2017
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2280
Subject(s) - static random access memory , leakage (economics) , access time , electronic engineering , leakage power , random access memory , electrical engineering , degradation (telecommunications) , computer science , transistor , engineering , computer hardware , voltage , economics , macroeconomics
Summary A novel sub‐threshold 9 T Static Random Access Memory (SRAM) cell designed and simulated in 14‐nm FinFET technology is proposed in this paper. The proposed 9 T‐SRAM cell offers an improved access time in comparison to the 8 T‐SRAM cell. Furthermore, an assist circuit is proposed by which the leakage current of the proposed SRAM cell is reduced by 20% when holding ‘0’ and an equal leakage current during hold ‘1’ in comparison to the 8 T‐SRAM cell. The proposed circuit improves the access time by 40% in comparison to the 8 T‐SRAM cell without any degradation in write and read noise margins, as well. The maximum operating frequency of the proposed SRAM cell is 1.53 MHz at V DD = 270 mV. Copyright © 2016 John Wiley & Sons, Ltd.