Premium
An 11‐μ W, 9‐bit fully differential, cyclic/algorithmic ADC in 0.13 μm CMOS
Author(s) -
Bako Niko,
Fricke Kyle,
Sobot Robert,
Baric Adrijan
Publication year - 2017
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2278
Subject(s) - cmos , integral nonlinearity , operational amplifier , flash adc , capacitor , voltage , effective number of bits , amplifier , electrical engineering , switched capacitor , physics , successive approximation adc , 12 bit , electronic engineering , voltage reference , engineering , converters
Summary This paper describes a fully differential, cyclic, analogue‐to‐digital converter (ADC). It utilizes a 4‐bit binary weighted capacitor array to obtain 9‐bit resolution. The ADC uses an operational amplifier to suppress supply voltage variations. The operational amplifier with the slew‐rate detection is used to increase the speed of the ADC. The ADC is fabricated in IBM 0.13 μm CMOS process and occupies 650 × 850μm 2 active area. At 10 kS/s sampling rate, the ADC consumes 11 μW. In order to test immunity of the ADC on the supply voltage variations, static and dynamic performance of the ADC is measured with triangular supply voltage ( V D C = 1.5 V, V A C = 200m V pp , f = 1 kHz). The measured peak of differential nonlinearity and integral nonlinearity is + 0.26/ − 0.67 and + 0.65/ − 0.59, respectively. At 250 Hz, effective number of bit is 8.4 bits, S F D R = 66.7 dB and S N D R = 52.6 dB. Copyright © 2016 John Wiley & Sons, Ltd.