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Delay‐locked loop based clock and data recovery with wide operating range and low jitter in a 65‐nm CMOS process
Author(s) -
Wang Yuan,
Liu Yuequan,
Jia Song,
Zhang Xing
Publication year - 2017
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2267
Subject(s) - jitter , cmos , delay locked loop , phase locked loop , loop (graph theory) , block (permutation group theory) , electronic engineering , computer science , voltage , physics , electrical engineering , engineering , mathematics , geometry , combinatorics
Summary A delay‐locked loop (DLL) based clock and data recovery (CDR) circuit with a half‐rate clock is proposed. The CDR includes a coarse and a fine tuned block, in which the novel coarse and fine phase detectors form closed loops. It is designed in a 65‐nm complementary metal‐oxide semiconductor (CMOS) process using a 1.2‐V supply voltage. The simulation results show that it can cover a wide operating range from 500 Mbps to 8 Gbps and the corresponding peak‐to‐peak jitters are 1.63 ps and 0.96 ps, respectively. Copyright © 2016 John Wiley & Sons, Ltd.