Delay‐locked loop based clock and data recovery with wide operating range and low jitter in a 65‐nm CMOS process

Summary A delay‐locked loop (DLL) based clock and data recovery (CDR) circuit with a half‐rate clock is proposed. The CDR includes a coarse and a fine tuned block, in which the novel coarse and fine phase detectors form closed loops. It is designed in a 65‐nm complementary metal‐oxide semiconductor (CMOS) process using a 1.2‐V supply voltage. The simulation results show that it can cover a wide operating range from 500 Mbps to 8 Gbps and the corresponding peak‐to‐peak jitters are 1.63 ps and 0.96 ps, respectively. Copyright © 2016 John Wiley & Sons, Ltd.