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Application of class D power amplifiers in low power potentiostat circuits
Author(s) -
Habibi Mehdi,
Ghanbari Sonia
Publication year - 2017
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2240
Subject(s) - potentiostat , amplifier , electronic engineering , comparator , electrical engineering , cmos , dissipation , operational amplifier , power (physics) , engineering , capacitor , computer science , control theory (sociology) , voltage , physics , control (management) , electrode , quantum mechanics , artificial intelligence , electrochemistry , thermodynamics
Summary In this paper a low power CMOS potentiostat is presented for energy limited applications such as human implantable sensors. The main focus is on using different techniques to reduce the power consumption at different circuit blocks, especially in the output stage that delivers power to the electrochemical cell. The proposed technique includes the use of a class D amplifier to reduce conduction power dissipation compared with conventional linear methods. Power dissipation has been improved by several other considerations such as elimination of opamp blocks which consume static power, avoiding current sampling stages and using dynamic latched comparators for loop error calculations. Closed loop stability problem and a low power solution to overcome this issue are addressed in the paper. The role of effective parameters such as inductor value, output MOSFET dimensions and clock pulse timing has been investigated and optimization considerations are used to achieve the low power potentiostat. Evaluation results show that a 12.96‐μW potentiostat with 1.03‐μW power dissipation and 89% efficiency is achievable with a linearity of R 2 = 0.998. Copyright © 2016 John Wiley & Sons, Ltd.