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A single‐bit continuous‐time delta‐sigma modulator using clock‐jitter and inter‐symbol‐interference suppression technique
Author(s) -
Sabouhi Vahid,
Aghdam Esmaeil Najafi,
Saeedi Saeed
Publication year - 2017
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2224
Subject(s) - jitter , oversampling , delta sigma modulation , waveform , electronic engineering , cmos , sampling (signal processing) , noise (video) , electrical engineering , computer science , engineering , filter (signal processing) , voltage , artificial intelligence , image (mathematics)
Summary This paper presents a technique for mitigating two well‐known DAC non‐idealities in continuous‐time delta‐sigma modulators (CTDSMs), particularly in wide‐band and low over‐sampling‐ratio (OSR) cases. This technique employs a special digital‐to‐analog convertor (DAC) waveform, called modified return‐to‐zero (MRZ), to reduce the time uncertainty effect because of the jittered clock at the sampling time instances and eliminate the effect of inter‐symbol‐interference (ISI) which degrades the modulator performance, especially when non‐return‐to‐zero (NRZ) DAC waveform is chosen in the modulator design. A third‐order single‐bit CTDSM is designed based on the proposed technique and step‐by‐step design procedure at circuit and system levels, considering clock jitter and ISI, is explained. Circuit simulations in 180‐nm CMOS technology show that in the presence of circuit non‐idealities which generate jitter and asymmetrical rise and fall times in the DAC current pulse, signal‐to‐noise‐distortion‐ratio (SNDR) of the proposed modulator is higher than the conventional modulator with NRZ waveform by about 10 dB. In these simulations, clock jitter standard deviation is 0.3% of the sampling period (T S ) and the difference between fall/rise times in the DAC current pulse is 4%T S . Simulated at 600‐MHz sampling frequency (f S ) with an oversampling ratio (OSR) of 24, SNDR figure of merit (FOM SNDR ) of the proposed modulator in 180‐nm CMOS is 300 fj/conversion. Copyright © 2016 John Wiley & Sons, Ltd.