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A true single‐phase clock dual‐modulus prescaler with enhanced robustness against leakage currents
Author(s) -
Jia Song,
Wang Ziyi,
Yan Shilin,
Wang Yuan
Publication year - 2016
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2196
Subject(s) - leakage (economics) , robustness (evolution) , frequency divider , transistor , electronic engineering , leakage power , voltage , electrical engineering , computer science , engineering , cmos , biochemistry , chemistry , macroeconomics , economics , gene
Summary A new leakage‐tolerant true single‐phase clock dual‐modulus prescaler based on a stage‐merged scheme is presented. Leakage‐restricting transistors are used to reduce the leakage currents at critical nodes, and leakage‐related malfunctions are eliminated at minimal cost in terms of speed, power, and area overheads. An HSPICE simulation in a 40‐nm process shows that the proposed divide‐by‐2/3 divider can effectively enhance robustness against leakage currents to extend the low frequency limit of the circuit over wide temperature and threshold voltage ranges. Additionally, the proposed design shows speed and power performance that is comparable with the performance levels of referenced designs. Copyright © 2016 John Wiley & Sons, Ltd.