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Low‐cost multi‐standard simultaneous forward and inverse video transform core
Author(s) -
Tseng YunHua,
Chen YuanHo,
Kao TzeYang,
Lu ChihWen
Publication year - 2016
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2180
Subject(s) - discrete cosine transform , discrete hartley transform , adder , computer science , dimension (graph theory) , overhead (engineering) , inverse , discrete fourier transform (general) , algorithm , computer hardware , arithmetic , mathematics , fourier transform , image (mathematics) , fractional fourier transform , artificial intelligence , telecommunications , latency (audio) , fourier analysis , mathematical analysis , geometry , pure mathematics , operating system
Summary This paper presents a cost‐effective, two‐dimensional (2‐D) discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) capable of MPEG1/2/4, H.264 4 × 4/8 × 8, and VC‐1 4 × 4/8 × 8/4 × 8/8 × 4 standards. We developed multilevel factor sharing in conjunction with distributed arithmetic in a scheme referred to as common sharing distributed arithmetic to enable sharing of the coefficient matrix circuit and replace multipliers with adders and shifters. By taking advantage of the similarities between DCT and IDCT transforms, we were able to implement an interlaced sorting method in a single circuit of the DCT and IDCT transform core in order to reduce area overhead while enabling the simultaneous operation of DCT and IDCT. The proposed design arranges the data of the first dimension and second dimension in order to reuse the same 1‐D core to compute 2‐D data. In this manner, first dimension and second dimension data of DCT and IDCT can be processed simultaneously in a single transform core. The efficacy of the proposed approach has been verified by fabricating a test chip using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 µm complementary metal‐oxide semiconductor process. The inverse transform core was shown to have an operating frequency of 227 MHz and throughput of 454 Mpel/s with a gate count of 32.5 k. Copyright © 2015 John Wiley & Sons, Ltd.