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Efficient power pad assignment for multi‐voltage SoC and its application in floorplanning
Author(s) -
Chu Zhufei,
Xia Yinshui,
Wang Lunyao,
Wang Jian
Publication year - 2016
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2178
Subject(s) - floorplan , voltage , benchmark (surveying) , voltage drop , power integrity , power (physics) , electronic engineering , computer science , engineering , electrical engineering , embedded system , signal integrity , physics , geodesy , quantum mechanics , geography , printed circuit board
Summary Multi‐voltage techniques are being developed to improve power savings by providing lower supply voltages for noncritical blocks under the performance constraint. However, the resulted lower voltage drop noise margin brings serious obstacles in power/ground (P/G) network design of the wire‐bonding package. For voltage drop optimization, both block and power pad positions are important factors that need to be considered. Traditional multi‐voltage floorplanning methods use rough estimation to evaluate the P/G network resource without considering the locations of power pads. To remedy this deficiency, in this paper, an efficient voltage drops aware power pad assignment (PPA) method is proposed, and it is further integrated into a floorplanning algorithm. We first present a fast PPA method for each power domain by the spring model. Then, to evaluate voltage drops during floorplanning iterations, the weighted distance from the blocks to the power pads is adopted as an optimization objective instead of time‐consuming matrix computation. Experimental results on Gigascale System Research Center (GSRC) benchmark circuits indicate that the proposed method generates an optimized placement of power pads and floorplanning of blocks with high efficiency. Copyright © 2015 John Wiley & Sons, Ltd.