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Clock gating methodologies and tools: a survey
Author(s) -
Pouiklis Georgios,
Sirakoulis Georgios Ch.
Publication year - 2016
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2107
Subject(s) - computer science , design flow , clock gating , systems engineering , power consumption , automation , reliability engineering , electronic design automation , software engineering , computer architecture , power (physics) , embedded system , engineering , clock signal , clock skew , telecommunications , jitter , mechanical engineering , physics , quantum mechanics
Summary Clock gating (CG) is a widely used design method for reducing the dynamic power consumption in digital circuits. Although it is a mature technique, theoretical work and tools for its application are still evolving and considered a matter of ongoing research, due to its significant effect in the overall power of the designs under study. This paper introduces a detailed review of the spectrum of CG approaches, theoretical and practical, from an architectural and register transfer level to synthesis, place and route, and testing issues. Furthermore, tools availability, limitations, and requirements concerning CG are examined for each design flow step. Conclusively, an evaluation of the presented techniques and literature is provided, estimating their usefulness and identifying areas for future research, exploration, and automation. Copyright © 2015 John Wiley & Sons, Ltd.