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A small fully digital open‐loop clock and data recovery circuit for wired BANs
Author(s) -
Derogarian Fardin,
Ferreira João Canas,
Tavares Vítor Grade
Publication year - 2016
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2092
Subject(s) - clock domain crossing , synchronous circuit , clock skew , jitter , clock generator , digital clock manager , computer science , clock signal , clock recovery , cpu multiplier , self clocking signal , phase locked loop , electronic engineering , clock gating , clock synchronization , asynchronous circuit , synchronization (alternating current) , engineering , channel (broadcasting) , telecommunications
Summary This paper proposes a new open‐loop and low complexity (small size) fast‐lock synchronization circuit for clock and data recovery in wearable systems. The system includes sensors embedded in textile and connected by conductive yarns. Synchronization is based on the open‐loop selection of the correct phase of the receiver clock synchronously with the incoming signal. The clock generator of the receiver is an autonomous oscillator set to operate at the same nominal frequency. The circuit lock time is at most one clock cycle, faster than all methods based on phase‐locked loops or delay‐locked loops. The circuit can be used for baseband communication independently of the signal coding method used in the physical layer, making it suitable for many applications. The fully digital circuit (including non‐return‐to‐zero inverted decoder) occupies 0.0022 in a 0.35 complementary metal‐oxide semiconductor (CMOS) process, a smaller implementation than many existing circuits, and supports a maximum system clock frequency of 70 for a 35‐data rate. Experimental results demonstrate that the proposed circuit robustly generates a synchronous clock for data recovery. The circuit is suitable for systems that tolerate some jitter but requires fast lock time, small size, and low energy consumption. Copyright © 2015 John Wiley & Sons, Ltd.