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A 6‐Gbps/lane receiver for a clock‐forwarded link in 65‐nm CMOS process
Author(s) -
Ahn KeunSeon,
Yoo Changsik
Publication year - 2015
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.2080
Subject(s) - wireline , cmos , phase locked loop , sampling (signal processing) , clock recovery , jitter , electronic engineering , computer science , clock domain crossing , sample and hold , electronic circuit , engineering , clock signal , electrical engineering , synchronous circuit , telecommunications , detector , wireless
Summary For a 6‐Gbps/lane clock‐forwarded link, a wireline receiver has been developed. The phases of the sampling clocks are aligned to the center of the input data eye by a clock and data recovery (CDR) circuit. In the CDR circuit, the sampling clock phases are rotated by a phase rotating phase locked loop (PLL). A three‐tap decision feedback equalizer (DFE) compensates for the loss of cable together with a continuous‐time linear equalizer (CTLE) to ensure sufficient eye opening for the CDR circuit to find the optimum sampling phase. The DFE coefficients are adaptively calculated based on the data and edge samples. Implemented in a 65‐nm CMOS process, the three‐lane 6‐Gbps/lane receiver for a clock‐forwarded link occupies 0.63 mm 2 including pads and consumes 288 mA from a 1.2‐V supply. Copyright © 2015 John Wiley & Sons, Ltd.